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89HPES6T6G2 (Low latency cut-through switch architecture )
89HPES6T6G2首页预览图
型号: 89HPES6T6G2
PDF文件:
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功能描述: Low latency cut-through switch architecture
PDF文件大小: 600.79 Kbytes
PDF页数: 共30页
制造商: IDT[Integrated Device Technology]
制造商LOGO: IDT[Integrated Device Technology] LOGO
制造商网址: http://www.idt.com
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100%
1 of 30 March 30, 2011
© 2011 Integrated Device Technology, Inc.
DSC 6930
®
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
Device Overview
The 89HPES6T6G2, a 6-lane 6-port Gen2 PCI Express® switch, is a
member of IDT’s PRECISE™ family of PCI Express switching solutions.
The PES6T6G2 is a peripheral chip that performs PCI Express Base
switching with a feature set optimized for servers, storage, communica-
tions, and consumer applications. It provides connectivity and switching
functions between a PCI Express upstream port and five downstream
ports or peer-to-peer switching between downstream ports.
Features
High Performance PCI Express Switch
Six Gen2 PCI Express lanes supporting 5 Gbps and
2.5 Gbps operation
One x1 upstream port
Five x1 downstream ports
Low latency cut-through switch architecture
Support for Max Payload Size up to 2Kbytes
Supports one virtual channel and eight traffic classes
PCI Express Base Specification Revision 2.0 compliant
Flexible Architecture with Numerous Configuratio n Options
Automatic lane reversal on all ports
Automatic polarity inversion
Supports in-band hot-plug presence detect capability
Supports external signal for hot plug event notification allowing
SCI/SMI generation for legacy operating systems
Configurable downstream port PCI-to-PCI bridge device
numbering
Crosslink support
Supports ARI forwarding defined in the Alternative Routing-ID
Interpretation (ARI) ECN for virtualized and non-virtualized
environments
Ability to load device configuration from serial EEPROM
Legacy Support
PCI compatible INTx emulation
Supports bus locked transactions, allowing use of PCI Express
with legacy software
Highly Integrated Solution
Requires no external components
Incorporates on-chip internal memory for packet buffering and
queueing
Integrates six 5 Gbps / 2.5 Gbps embedded SerDes, 8B/10B
encoder/decoder (no separate transceivers needed)
Reliability, Availability, and Serviceability (RAS) Features
Ability to disable peer-to-peer communications
Supports ECRC and Advanced Error Reporting
All internal data and control RAMs are SECDED ECC
protected
Supports PCI Express hot-plug on all downstream ports
Supports upstream port hot-plug
Hot-swap capable I/O
External Serial EEPROM contents are checksum protected
Block Diagram
Figure 1 Internal Block Diagram
6-Port Switch Core / 6 Gen2 PCI Express Lanes
Frame Buffer Route Table
Port
Arbitration
Scheduler
SerDes
Phy
Logical
Layer
Multiplexer / Demultip lexer
Transaction Layer
Data Link Layer
SerDes
Phy
Logical
Layer
Multiplexer / Demultip lexer
Transaction Layer
Data Link Layer
SerDes
Phy
Logical
Layer
Multiple xer / De mu ltip le xe r
Transaction Layer
Data Link Layer
(Port 0)
(Port 1)
(Port 5)
89HPES6T6G2
Data Sheet
6-Lane 6-Port
Gen2 PCI Express® Switch
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