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XC5VLX110-1FFG1760I

日期:2020-06-28 11:24    发布企业: 深圳市意好科技有限公司

深圳市意好科技有限公司  vip会员

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       使用第二代ASMBL™ (高级硅模块)基于列的架构,Virtex-5系列包含五个

独特的平台(子系列),任何一个FPGA系列提供的最多选择。每个平台包含不同比例的功能

各种先进逻辑设计的需要。除了最先进的高性能逻辑结构,Virtex-5fpgas

包含许多硬IP系统级块,包括强大的36kbit块RAM/FIFOs、第二代25x18DSP片,

选择™ 内置数字控制阻抗芯片同步技术™ 源同步接口块,系统监视器

功能,增强的时钟管理模块,集成了DCM(数字时钟管理器)和锁相环(PLL)时钟

生成器和高级配置选项。附加的平台相关功能包括功率优化的高速串行

用于增强串行连接的收发器模块、PCI Express®兼容的集成端点模块、三模式以太网Mac(媒体

访问控制器)和高性能PowerPC®440微处理器嵌入式模块。这些特性允许高级逻辑

设计人员将最高级别的性能和功能构建到基于FPGA的系统中。基于65纳米的最新技术

铜工艺技术,Virtex-5fpgas是定制ASIC技术的可编程替代品。最先进的系统设计

要求FPGAs的可编程强度。Virtex-5fpgas为满足高性能逻辑的需求提供了最佳的解决方案

设计师,高性能的数字信号处理器设计师,以及具有前所未有的逻辑的高性能嵌入式系统设计师,数字信号处理器,

硬/软微处理器和连接能力。Virtex-5lxt、SXT、TXT和FXT平台包括高级高速

串行连接和链路/事务层功能。

Virtex-5fpga特性综述

•五个平台LX、LXT、SXT、TXT和FXT

-Virtex-5lx:高性能通用逻辑应用

——Virtex-5 LXT:高性能逻辑和高级串行

连接性

-Virtex-5 SXT:高性能信号处理

具有高级串行连接的应用程序

-Virtex-5 TXT:高性能双通道系统

密度高级串行连接

-Virtex-5 FXT:高性能嵌入式系统

高级串行连接

•跨平台兼容性

-LXT、SXT和FXT设备在

使用可调电压调节器的同一封装

•最先进、高性能、最佳利用率,

现场可编程门阵列结构

-真正的6输入查找表(LUT)技术

-双5-LUT选项

-改进的减少跳路由

-64位分布式RAM选项

-SRL32/双SRL16选项

•强大的时钟管理磁贴(CMT)时钟

-用于零延迟的数字时钟管理器(DCM)块

缓冲、频率合成和时钟移相

-用于输入抖动滤波、零延迟缓冲的PLL块,

频率合成和相位匹配时钟分割

•36 Kbit块RAM/FIFOs

-真正的双端口RAM块

-增强的可选可编程FIFO逻辑

-可编程

-真正的双端口宽度高达x36

-简单的双端口宽度高达x72

-内置可选纠错电路

-可选地将每个块编程为两个独立的18 Kbit

阻碍

•高性能并行选择技术

-1.2至3.3V I/O操作

使用芯片同步的源同步接口™

技术

-数字控制阻抗(DCI)有源终端

-灵活的细粒度I/O银行

-高速存储器接口支持

•高级DSP48E切片

-25 x 18,二补,乘法

-可选的加法器、减法器和累加器

-可选管道

–可选的按位逻辑功能

-专用级联连接

•灵活的配置选项

-SPI和并行闪存接口

-支持专用回退的多比特流

重构逻辑

-自动总线宽度检测能力

•所有设备上的系统监控能力

片上/片外热监测

片上/片外电源监控

-JTAG访问所有监测数量

•用于PCI Express设计的集成端点块

-LXT、SXT、TXT和FXT平台

-符合PCI Express基本规范1.1

每个街区的x1、x4或x8车道支持

-与RocketIO合作™ 收发器

•三模式10/100/1000 Mb/s以太网Mac

-LXT、SXT、TXT和FXT平台

-RocketIO收发器可以用作物理层或连接到

使用多个软MII(媒体无关)的外部PHY

接口)选项

•RocketIO GTP收发器100 Mb/s至3.75 Gb/s

-LXT和SXT平台

•RocketIO GTX收发器150 Mb/s至6.5 Gb/s

-TXT和FXT平台

•PowerPC 440微处理器

-仅限FXT平台

-RISC架构

-7级管道

-包括32 Kbyte指令和数据缓存
General Description Using the second generation ASMBL™ (Advanced Silicon Modular Block) column-based architecture, the Virtex-5 family contains five distinct platforms (sub-families), the most choice offered by any FPGA family. Each platform contains a different ratio of features to address the needs of a wide variety of advanced logic designs. In addition to the most advanced, high-performance logic fabric, Virtex-5 FPGAs contain many hard-IP system level blocks, including powerful 36-Kbit block RAM/FIFOs, second generation 25 x 18 DSP slices, SelectIO™ technology with built-in digitally-controlled impedance, ChipSync™ source-synchronous interface blocks, system monitor functionality, enhanced clock management tiles with integrated DCM (Digital Clock Managers) and phase-locked-loop (PLL) clock generators, and advanced configuration options. Additional platform dependant features include power-optimized high-speed serial transceiver blocks for enhanced serial connectivity, PCI Express® compliant integrated Endpoint blocks, tri-mode Ethernet MACs (Media Access Controllers), and high-performance PowerPC® 440 microprocessor embedded blocks. These features allow advanced logic designers to build the highest levels of performance and functionality into their FPGA-based systems. Built on a 65-nm state-of-the-art copper process technology, Virtex-5 FPGAs are a programmable alternative to custom ASIC technology. Most advanced system designs require the programmable strength of FPGAs. Virtex-5 FPGAs offer the best solution for addressing the needs of high-performance logic designers, high-performance DSP designers, and high-performance embedded systems designers with unprecedented logic, DSP, hard/soft microprocessor, and connectivity capabilities. The Virtex-5 LXT, SXT, TXT, and FXT platforms include advanced high-speed serial connectivity and link/transaction layer capability. Summary of Virtex-5 FPGA Features • Five platforms LX, LXT, SXT, TXT, and FXT − Virtex-5 LX: High-performance general logic applications − Virtex-5 LXT: High-performance logic with advanced serial connectivity − Virtex-5 SXT: High-performance signal processing applications with advanced serial connectivity − Virtex-5 TXT: High-performance systems with double density advanced serial connectivity − Virtex-5 FXT: High-performance embedded systems with advanced serial connectivity • Cross-platform compatibility − LXT, SXT, and FXT devices are footprint compatible in the same package using adjustable voltage regulators • Most advanced, high-performance, optimal-utilization, FPGA fabric − Real 6-input look-up table (LUT) technology − Dual 5-LUT option − Improved reduced-hop routing − 64-bit distributed RAM option − SRL32/Dual SRL16 option • Powerful clock management tile (CMT) clocking − Digital Clock Manager (DCM) blocks for zero delay buffering, frequency synthesis, and clock phase shifting − PLL blocks for input jitter filtering, zero delay buffering, frequency synthesis, and phase-matched clock division • 36-Kbit block RAM/FIFOs − True dual-port RAM blocks − Enhanced optional programmable FIFO logic − Programmable - True dual-port widths up to x36 - Simple dual-port widths up to x72 − Built-in optional error-correction circuitry − Optionally program each block as two independent 18-Kbit blocks • High-performance parallel SelectIO technology − 1.2 to 3.3V I/O Operation − Source-synchronous interfacing using ChipSync™ technology − Digitally-controlled impedance (DCI) active termination − Flexible fine-grained I/O banking − High-speed memory interface support • Advanced DSP48E slices − 25 x 18, two’s complement, multiplication − Optional adder, subtracter, and accumulator − Optional pipelining − Optional bitwise logical functionality − Dedicated cascade connections • Flexible configuration options − SPI and Parallel FLASH interface − Multi-bitstream support with dedicated fallback reconfiguration logic − Auto bus width detection capability • System Monitoring capability on all devices − On-chip/Off-chip thermal monitoring − On-chip/Off-chip power supply monitoring − JTAG access to all monitored quantities • Integrated Endpoint blocks for PCI Express Designs − LXT, SXT, TXT, and FXT Platforms − Compliant with the PCI Express Base Specification 1.1 − x1, x4, or x8 lane support per block − Works in conjunction with RocketIO™ transceivers • Tri-mode 10/100/1000 Mb/s Ethernet MACs − LXT, SXT, TXT, and FXT Platforms − RocketIO transceivers can be used as PHY or connect to external PHY using many soft MII (Media Independent Interface) options • RocketIO GTP transceivers 100 Mb/s to 3.75 Gb/s − LXT and SXT Platforms • RocketIO GTX transceivers 150 Mb/s to 6.5 Gb/s − TXT and FXT Platforms • PowerPC 440 Microprocessors − FXT Platform only − RISC architecture − 7-stage pipeline − 32-Kbyte instruction and data caches included − Optimized processor interface structure (crossbar) • 65-nm copper CMOS process technology • 1.0V core voltage • High signal-integrity flip-chip packaging available in standard or Pb-free package options 


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